//https://hdlbits.01xz.net/wiki/Tb/and
`timescale 1ps / 1ps
 
module top_module();
    reg [1:0]in;
    wire	 out;
    
    andgate u_andgate(
        .in     (in    ),
        .out	(out   )
    );
    
    initial begin
        in = 2'b00;
        #10;
        in = 2'b01;
        #10;
        in = 2'b10;
        #10;
        in = 2'b11;
    end  
 
    /*
    initial begin
        in[1] = 1'b0;
        in[0] = 1'b0;
        #10;
        in[1] = 1'b0;
        in[0] = 1'b1;
        #10;
        in[1] = 1'b1;
        in[0] = 1'b0;
        #10;
        in[1] = 1'b1;
        in[0] = 1'b1;
    end
    */
        
endmodule